Memory devices, such as dynamic random access memories (“DRAMs”) contain a large number of memory cells arranged in arrays having rows and columns. A memory cell is selected by a row address and a column address. The row address designates the row of the array containing the selected memory cell, and the column address designates the column of the array containing the selected memory cell. A series of memory cells can be selected by sequentially applying respective addresses to the memory device. However, it requires a significant period of time to decode and process each memory address, thereby slowing the rate at which the memory cells in the series can be selected. Furthermore, the need to generate a respective address to access each memory cell also slows the rate at which memory cells can be accessed and increases the processing overhead of circuitry interfacing with the memory device.
To avoid or at least alleviate the above-described problems, various modes have been devised to avoid the need to provide a row address and a column address for each memory access. For example, in a “page mode” access to a DRAM, a single row address is applied to the DRAM to select a row or “page” of memory cells. A sequence of column addresses is then applied to the DRAM to select a corresponding sequence of memory cells in respective columns in the selected row.
Although page mode memory accesses have the advantage of eliminating the need for a respective row address to access each of the memory cells except for the first memory cell, the time required to decode and process each column address nevertheless requires a significant amount of time. To eliminate the need to apply a column address to the memory device to access each memory cell, “burst mode” memory devices have been developed. In a burst mode memory device, such as a burst mode DRAM, a starting row address and a starting column address are applied to the DRAM. The DRAM then activates the row of memory cells corresponding to the row address and internally generates a sequence of column addresses to access respective memory cells in the activated row. Burst access modes significantly increase the rate at which data may be read from or written to a memory device.
Burst mode memory devices initially operated by serially accessing the memory cells in an active row. However, with the advent of synchronous DRAM (“SDRAMs”) having two separately addressable arrays of memory cells, interleave memory accesses were introduced. In interleave memory accesses, the memory addresses increment by toggling the least significant bit (“LSB”) every address, toggling the next to least significant bit (“NLSB”) every other address, toggling the next most significant bit every fourth address, etc. To further increase memory access speeds, a 2-bit prefetch mode of operation was developed. In the 2-bit prefetch mode of operation, the LSB of an address is ignored, and corresponding columns in respective arrays are thus simultaneously accessed using the address designated by all but the LSB of the column address. The column that is accessed in each array is thus designated by the NLS and higher bits and, as a practical matter, should be the same for both arrays so that corresponding columns in both arrays are simultaneously accessed.
As explained in greater detail below, the burst mode addressing sequence for a memory device is different in the interleave mode than it is in the serial mode. Furthermore, the difficulties of accommodating both the serial mode and the interleave mode are exacerbated by operation in the 2-bit prefetch mode. In the 2-bit prefetch mode, a memory cell in an odd memory array (normally designated by an odd address) and a memory cell in an even memory array (normally designated by an even address) should be simultaneously accessed. In such cases, as previously explained, the least significant bit (“LSB”) of a starting memory address is ignored because the LSB normally designates either an even memory array or an odd memory array.
The sequence of column addresses that should be generated starting at an initial, externally applied column address of “CAN . . . CA2, CA1, CA0” (where “CA0” is the LSB, “CA1” is the NLSB, and “CAN . . . CA2” are higher order bits) are shown below (ignoring the bits that are higher order than CA3). The address sequence for an interleave mode with a starting column address of “0 1 1 0” is as follows:
“0 1 1 0”(starting column address)“0 1 1 1”“1 0 0 0”“1 0 0 1”“1 0 1 0”“1 0 1 1”“1 1 0 0”“1 1 0 1”
The address sequence for an interleave mode with a starting column address of “0 1 0 1” is as follows:
“0 1 0 1”(starting column address)“0 1 0 0”“0 1 1 1”“0 1 1 0”“1 0 0 1”“1 0 0 0”“1 0 1 1”“1 0 1 0”
The address sequence for a serial mode with a starting column address of “0 1 1 0” is as follows:
“0 1 1 0”(starting column address)“0 1 1 1”“1 0 0 0”“1 0 0 1”“1 0 1 0”“1 0 1 1”“1 1 0 0”“1 1 0 1”
In all cases, the LSB in all of the above examples is ignored by the memory devices, as previously explained. In each of the above examples, the NLS and higher bits select the same column in each pair of addresses, and the LSB, is effectively “0” for the even array and “1” for the odd array. For example, the first pair of column addresses in the interleave mode with a starting column address of “0 1 1 0” selects a column in both arrays having a NLSB (i.e., an effective LSB) of “1”, and the second pair of column addresses selects a column in both arrays having a NLSB (i.e., an effective LSB) of “0 ”.
In all of the above cases, the sequence of column addresses can be generated by an incrementing a burst counter that generates only the NLSB and all bits more significant than the NLSB since the LSB is ignored by the counter. Note, however, a problem that develops in the serial mode where the starting column address is “0 1 0 1”:
“0 1 0 1”(starting column address)“0 1 1 0”“0 1 1 1”“1 0 0 0”“1 0 0 1”“1 0 1 0”“1 0 1 1”“1 1 0 0”
In this case, the NLSB selects a different column in each pair of column addresses. For example, the “0” NLSB bit of the first column address in the first pair of addresses selects a column in one array designated by an address ending in “0” and the “1” NLSB bit of the second column address in the first pair of addresses selects a column in the other array designated by an address ending in “1.” Similarly, the “1” NLSB bit of the first column address in the second pair of addresses selects a column in one array designated by an address ending in “1” and the “0” NLSB bit of the second column address in the second pair of addresses selects a column in the other array designated by an address ending in “0.” As a result, the two bits of accessed data are stored in different columns of the arrays, thus making it difficult to subsequently access the same two bits of data.
Similarly, in the interleave mode with a starting column address of “0 0 1 1” the address sequence must be as follows:
“0 0 1 1”(starting column address)“0 0 1 0”“0 0 0 1”“0 0 0 0”“0 1 1 1”“0 1 1 0”“0 1 0 1”“0 1 0 0”
The above address sequence cannot be generated by serial increment of a burst counter since the addresses in the above sequence (again, ignoring the LSB) do not increment. Thus, an interleave sequence for certain starting addresses cannot be generated in the 2-bit prefetch mode by simply incrementing a burst counter.
Conventional burst mode 2-bit prefetch memory devices capable of operating in either a serial mode or an interleave mode generally require two different burst mode counters, one of which is used in the serial mode and the other of which is used in the interleave mode. The need for separate burst accessing circuitry for each of these two burst modes significantly increases the cost of memory devices operating in these two modes.
There is therefore a need for a burst mode column addressing circuit and method for a 2-bit prefetch memory device that can operate in both a serial mode and an interleave mode thereby eliminating the need for separate addressing and counting circuitry for each mode.